Description of the project: Crossbar 3 to 8

Main description of the project.

The following document stands in order to show you a basic design of a crossbar with 3 inputs and 8 outpus. For now it's standing in the way the logic control, so you will suppose that any control signal is ok.

The general rules and objectives.

The task is to generate the physical design of digital logic module architecture investigating micro architecture and design. Producing such module in the electric tool in view of symbol, schematic and layout. Produce electrical simulations of the logical operation and maximum dynamic performance of the module; submit a written report and make an oral presentation of the design and implementation stages of the circuit.

1) Provide a block diagram representing the logical operation of the device (10 % ).

2) Investigate at least 2 different architectural implementations for module design and     justify why they chose that you implement (10 % )

3) Present the schematic diagram of the module (10 % )

4 ) Submit the completed layout of the module (20 % )

5) Provide a functional simulation 1 use case for the module (10 % )

6) Submit an electrical simulation show the maximum frequency of operation of the module ( 20 % )

7) Prepare a 20 minute demonstration for the class of your module and design ( 10%)

8) Include in the report the following information:

• Total area of the circuit.
• Count cells by cell type.
• Levels of metal used.
• Optimizations if any, would.

Comment on the main difficulty of the project.

First advance.

After to review the specs and functionality of the crossbar, it is a circuit that implements a kind of bit's rotator because the three inputs are going to be rotated according to the control signal asserted. The Figure 1 shows a preview.

First circuit design: S1,S2...S7 are control signals. X0,X1,X2 are inputs and Y0,Y1...Y7 outputs.

As you can see, this is a very simple design with only uses pass gates and ports, wires, and maybe some invertes for improving the exterior signals. The mapping table can be seen in the Table1.

Table1: Mapping table.

S7	S6	S5	S4	S3	S2	S1	S0	|	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0
0	0	0	0	0	0	0	1	|	Z	Z	Z	Z	Z	X2	X1	X0
0	0	0	0	0	0	1	0	|	Z	Z	Z	Z	X2	X1	X0	Z
0	0	0	0	0	1	0	0	|	Z	Z	Z	X2	X1	X0	Z	Z
0	0	0	0	1	0	0	0	|	Z	Z	X2	X1	X0	Z	Z	Z
0	0	0	1	0	0	0	0	|	Z	X2	X1	X0	Z	Z	Z	Z
0	0	1	0	0	0	0	0	|	X2	X1	X0	Z	Z	Z	Z	Z
0	1	0	0	0	0	0	0	|	X1	X0	Z	Z	Z	Z	Z	X2
1	0	0	0	0	0	0	0	|	X0	Z	Z	Z	Z	Z	X2	X1
								|
	Control Inputs							|		Data Outputs

It is intended to use the manhattan distribution for the layout design, but that is for the next advance. Also, I will recommend to read the next document, it is an extract to a very cool book and explain this very good: Chapter9.

References:

•  Notes of the Microelectronic course at Electrical Engineering School, UCR, Costa Rica.